SMT 4.0 and CTF

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AI Industry 4.0-aided manufacturing should incorporate CTF quality methodology.

Increased use and power of artificial intelligence-aided electronics manufacturing, such as Industry 4.0, creates the opportunity and need to revisit how one manages and improves quality and defect rates.

Traditionally, industry has relied on approaches such as acceptance sampling plans (ASP), Six Sigma (SS), and statistical process control (SPC). Although these approaches offer important data-driven tools to flag and correct the root causes of defects, they generally do so with equal emphasis attached to detecting any or all levels of defect criticality.

The problem with these methods is certain quality outcomes of primary significance to the customer can be missed, as the example below illustrates. This example
serves to illustrate how another strategic method can be cooperatively implemented that will help avoid catastrophic defects. We will label this approach as CTF (critical to function) testing.

In this article, we will address two different branches of CTF testing:

  1. The first branch addresses appropriately linking customer criticality to the RQL (reject quality level) assigned and used in implementing acceptance sampling plans (ASP).
  2. The second branch addresses satisfying customer CTF testing that appends to continuous process approaches. This includes AI failure detection methods installed in the new breed of assembly systems.

Using CTF Testing to Adjust Sampling Plan RQL

As an example, assume the very hypothetical case of a laptop density-type PCB with 500 components and 10,000 solder joints.

After the solder stencil step, the typical way to calculate the post-stencil current reject defect level (RDL) is to divide the number of missing, insufficient, open lead, and bridged solder deposits by the total number of solder deposits needed. Let’s say there’s solder missing or defective in 12 of the spots in the area where a large, expensive 1,000 I/O µBGA part is to reside. If we calculate the defect percentage as function of the total number of solder deposits (10,000), the RDL is 0.12%.

If the standard RQL set for this kind of “critical” defect is RQL = 1% (with AQL set close to 0.1%), then generally the process running with RDL = 0.12% will pass the ASP testing about 95% of the time. This would probably be considered acceptable by the manufacturer and passed on to solder reflow steps. All would be considered as a smooth flow until after the PCB bearing the large BGA was electrically tested, three to four process steps later, and discovered to be nonfunctional.

By the time this is discovered, the manufacturer has two uncomfortable choices: one, very expensive surgical-level rework; the other, to scrap the assembled board, incurring significant financial loss.

Once the manufacturer becomes aware there are post-soldering failures under this critical area, it should react by raising the screening tests to a more critical RQL level, say RQL = 0.1%, requiring the production line to target test to a lower AQL (AQL = 0.01%).

This first-level reaction would be very costly to the manufacturer.

However, if the manufacturer at product production launch has the customer identify the CTF areas, and if those areas receive the extra level of inspection pre-reflow solder of say 100%, then the future disastrous post-stencil PCB could be caught before the disaster. This approach would be less costly.

Using AI within Industry 4.0 Systems to Improve Quality and Yields

When a company adds or replaces older assembly equipment with newer-AI capable equipment, the process engineer plays a bigger role than they did with their previous level of responsibility. Before taking advantage of the power of the AI-capable equipment, the engineer needs to know what’s right and wrong and the critical control variables with the key process steps, such as PCB planarity, stencil print control and solder paste variations.

In performing this CTF failure analysis, the process engineer must document the procedure that predicts process failure percentage, depending on all major failure modes. This is generally done by running designed experiments. With the help of a statistician, the ranking and variability of the key sources of defects can be predicted. These factors should be quantified mathematically by how they affect the overall defect rate (in this case, 0.12%). What this means is critical factors have a higher weighting (0.12% or 6/12+6/12+0), whereas minor factors have a negligible weighting (for example, 0.05%).

If one has a stable process, this weighting will remain the same indefinitely. However, there are generally changes of equipment, materials, temperature and a whole host of factors that impact the ranking of the causative defects on a continuous basis. Therefore, the control parameters need to be factored into an updatable system. As a result, the constant changes in defect rankings expand the job of the process engineer.

The greater the changes in each factory, the greater the need to reweight the CTF failure equation on an ongoing basis. The process engineer would then pass a first-level equation to the software engineer for implementation in AI. The process engineer then becomes responsible for updating the equation. For example, a major soldering equipment change or repair would certainly require an update to the equation. So might a change in humidity. Additionally, the process engineer would also be responsible for any CTF failure modes that are introduced into the process.

Another new task for the project engineer would be to incorporate the capability of troubleshooting ongoing process failures. For example, leading-edge post-stencil AOI systems are capable of detecting CTF problems if the system is taught where to look and what to do when defects are discovered. Hence, if CTF testing can immediately address solder defects when any, even one, occurs in that large CTF µBGA area, then continuous screening as monitored by AOI systems can produce RDL to desired levels.

If the customer successfully helps the manufacturer identify the CTF areas in advance and designates tests that isolate those areas, then the future disastrous electrical test failures can be caught post-solder stencil. At this step in the process, affected PCBs can be washed and re-stenciled and reintroduced into the line before the placement and soldering of components.


Much of the PCB assembly community uses a reactive quality test method, measuring defects on a lot-by-lot basis. The negatives to this approach are larger numbers of rejected product and materials that cost excess money and the possibility of losing business.

Implementation of artificially intelligent systems introduces the capability of continuous process monitoring and reporting. This opens the door for process engineers to implement more rigorous process improvements, since increased data create increased knowledge of the sources of defects.

The process engineer plays an important role in new state AI. In the example presented, they must identify and categorize the 12 PCB spots by doing a rigorous defect analysis on those spots. This increased knowledge should also focus the engineer on determining whether they are CTF or not.

The CTF concept sounds simple to implement, but it requires closer involvement between the process team and the customer.

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